Intel May Deploy AVX-512 in Upcoming 10nm Cannon Lake CPUs

Intel is bringing its AVX-512 instruction set to desktop CPUs with its upcoming Cannon Lake CPUs, but AVX-512 is a good deal more complex than previous SIMD sets, and its capabilities are distributed across a wider range of products.

The post Intel May Deploy AVX-512 in Upcoming 10nm Cannon Lake CPUs appeared first on ExtremeTech.

The original article can be found here: https://www.extremetech.com/computing/257730-intel-may-deploy-avx-512-upcoming-10nm-cannon-lake-cpus?source=Computing

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ARM guns for high-performance computing with its new vector instruction set

Fujitsu PrimeHPC
ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses.

The original article can be found here: http://www.extremetech.com/extreme/234216-arm-guns-for-high-performance-computing-with-its-new-vector-instruction-set

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Soft Machines claims its cutting-edge VISC CPU cores can outperform Intel, ARM in performance per watt

VISC-Chip
Soft Machines has released new data on its VISC (Variable Instruction Set Computing) architecture, including performance data on how it should compare against current Intel and ARM CPUs. The company claims it can offer dramatic improvements in performance per watt by virtualizing the CPU itself.

The original article can be found here: http://www.extremetech.com/extreme/222516-soft-machines-claims-its-cutting-edge-visc-cpu-cores-can-outperform-intel-arm-in-performance-per-watt

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Apple's Beats by Dre support team debuts native Twitter videos

On Monday, Apple’s Beats by Dre began publishing product instruction videos directly to its customer support Twitter account, inserting brand awareness and outreach options directly into users’ chosen social media streams.

The original article can be found here: http://appleinsider.com.feedsportal.com/c/33975/f/616168/s/4883ec49/sc/28/l/0Lappleinsider0N0Carticles0C150C0A70C280Capples0Ebeats0Eby0Edre0Esupport0Eteam0Edebuts0Enative0Etwitter0Evideos0E/story01.htm

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RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source

Prototype RISC-V chip
A new instruction set by the original creator of MIPS aims to reinvent the ultra-low power, high-efficiency processor — and to do so with an architecture that’s fundamentally open and available to anyone who wants to build a chip. Can that approach succeed in the modern era?

The original article can be found here: http://www.extremetech.com/computing/188405-risc-rides-again-new-risc-v-architecture-hopes-to-battle-arm-and-x86-by-being-totally-open-source

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